A cache unit may be provided in association with a processor unit in a data processing apparatus, wherein the cache unit is configured to store local copies of data items accessed in a memory by the processor unit, so that if access to those data items is required again, the latency associated with accessing the data items stored in the memory can largely be avoided by instead accessing the local copy stored in the cache. When such later access to a cached data item is made and when this access is a write access that copy may then be updated in the cache and marked as such (“dirty”) in a write-back configuration, or the system may have a write-through configuration in which changes to data items in the cache are immediately propagated through to the original storage location in the memory.
In this context, the cache unit may have an allocation policy which determines its behaviour when a write miss occurs, i.e. when the processor unit seeks to write a data item to memory which is not currently cached in the cache unit. For example, in a data processing apparatus in which the reliability of the storage of data items is a significant factor, a “no-write allocate” policy may be used, according to which when a write miss occurs, the data item is caused to be written into the target memory without a copy of that data item also being pulled into the cache. Moreover, such a cache allocation policy may additionally be preferred because populating the cache with the data item will typically involve retrieving an entire cache line from the memory and it may be determined to be preferable to avoid the additional bus activity associated therewith.